In recent years, with advancement of semiconductor technology, programmable semiconductor devices as typified by FPGA (Field Programmable Gate Array) allowing the user to implement a desired function in a programmable manner in a short period have come into wide use.
As another type of programmable semiconductor device, there has also been proposed DRP (Dynamically Reconfigurable Processor) capable of dynamic reconfiguring the processing element units by improving their performance from gate level to processor level.
Under such circumstances, with the recent advancement of miniaturization technology, it has become possible to enlarge functions installed per one chip in a semiconductor device. However, accompanying an enlargement in functions, there may be deterioration in the delay and reliability in the interconnecting unit that connects the processing element units, thus causing a problem. Thus, there has recently been proposed insertion of a repeater into the interconnecting unit.
For example, Japanese Patent Laid-Open No. 2000-201066 (hereinafter referred to as Patent Document 1) proposes a programmable logic device having a bidirectional repeater arranged in an upper-level interconnecting resource thereof (refer to pp. 4-5, FIG. 2 of Patent Document 1).
More specifically, the programmable logic device disclosed in Patent Document 1, as shown in FIG. 1, includes processing element unit (PE) 1, input/output connection unit 2, interconnecting unit 3 connecting processing element unit (PE) via input/output connection unit 2, bidirectional repeater unit 4 arranged between the intersection points of interconnecting units 3, and selector 8 for changing the connection between processing element units (PE) 1. In the programmable logic device, direction control information for controlling bidirectional repeater unit 4 is preliminarily held in the memory element and based on direction control information, bidirectional repeater unit 4 is controlled to perform disconnection, or to drive interconnecting unit 3 in the forward direction or in the reverse direction.
Also, Japanese Patent No. 3284995 (hereinafter referred to as Patent Document 2) discloses a bidirectional bus repeater control device (refer to FIG. 1 of Patent Document 2) to control a bidirectional repeater using logical sum (OR) of bus driver control signals, and a bidirectional bus repeater control device (refer to FIG. 10 of Patent Document 2) having added thereto a logical product (AND) block to halt transmission of a bidirectional repeater control signal to the bidirectional repeater, and a bidirectional bus repeater control device (refer to FIGS. 19 and 21 of Patent Document 2) to control the bidirectional repeater by use of a cooperation dynamic buffer.
However, with respect to the programmable logic device disclosed in Patent Document 1, a bidirectional repeater and a control circuit (memory element and control wire) used for such a bidirectional repeater are required; thus the circuit area increases, causing a problem. More specifically, control wires and memory elements of a number corresponding to the number of circuit configuration patterns and bidirectional repeaters are needed.
Also, with respect to the bidirectional bus repeater control device disclosed in Patent Document 2, no technique for applying such bidirectional bus repeater control device to a programmable semiconductor device has been disclosed. Accordingly, it seems difficult to apply the bidirectional bus repeater control device to a programmable semiconductor device.